(1) Field of the Invention
The present invention relates to a method of fabricating a metal oxide semiconductor field effect transistor, (MOSFET), device, and more specifically to a method of reducing gate to substrate shorting during the metal silicide formation processes.
(2) Description of Prior Art
The semiconductor industry is continually striving to improve the performance of MOSFET devices. The ability to create devices with sub-micron features has allowed significant decreases, in performance degrading parasitic capacitances, and resistances, to be achieved, thus resulting in performance benefits. The attainment of sub-micron features has been accomplished via advances in several semiconductor fabrication disciplines. For example in photolithograhy the development of more sophisticated exposure cameras, as well as the use of more sensitive photoresist materials have allowed sub-micron features, in photoresist layers, to be routinely achieved. In addition the development of more advanced dry etching tools and processes have allowed the submicron images in photoresist layers to be successfully transferred to underlying materials used in MOSFET structures. In addition to contributions supplied by advances in MOSFET processing disciplines, performance improvements have also been realized via the use of more conductive materials. For example the use of polycide gate structures, a gate structure comprised of a metal silicide layer overlying a polysilicon layer, has significantly reduced the resistance of the gate structure, when compared to the previously used polysilicon gate structures. Polycide gate formation, when performed using a salicide process, (Self-ALigned-silICIDE), also results in the conductive metal silicide overlying source and drain regions, resulting in performance benefits.
The ability to achieve successful salicide formation dependent on the integrity of the insulator spacers, on the sides of the polysilicon gate structure, during the salicide formation procedure. For example prior to metal deposition, native oxide on the exposed top surface of the polysilicon gate structure, as well as the top surface of the source and drain region, has to be removed, to allow the subsequent metal silicide formation to be successful. Native oxide will prevent the reaction between the metal and the exposed silicon surfaces during an anneal cycle. Therefore a buffered hydrofluoric acid procedure is used prior to metal deposition. However if the insulator spacer, on the sides of the polysilicon gate structure, becomes defective, or significantly thinned, exposing polysilicon, as a result of the buffered hydrofluoric acid, metal pre-clean procedure, unwanted metal silicide formation, or metal silicide bridging, can occur on the sides of the polysilicon gate structure, resulting in gate to substrate shorting or leakages.
This invention will describe a process in which a double insulator spacer is used to prevent the metal silicide bridging phenomena, as well as allowing additional resistance decreases to be achieved via source and drain engineering procedures. After formation of a lightly doped source and drain region, a first, silicon oxide spacer is formed on the sides of the polysilicon gate, followed by the creation of a medium doped source and drain region. A second insulator spacer, silicon nitride, is then created, followed by the formation of a heavily doped source and drain region. A significant metal pre-clean procedure, using buffered hydrofluoric acid, can now be performed, without risking the integrity of the silicon nitride-silicon oxide spacer insulator, increasing the prospects of a successful salicide procedure. Prior art, such as Bracchita, et al, in U.S. Pat. No. 5,518,945, describe an insulator spacer, comprised of two materials, a silicon nitride-doped oxide composite. However that prior art does not teach the concept of creating two insulator spacers, allowing an additional source and drain procedure, to be performed between insulator spacer procedures.